In the field of semiconductor device design, it is well known to fabricate switching devices, for example, transistors, on silicon (Si) or other semiconductor materials. It is also known to form wells in the silicon by implanting ions of another element. Indeed, so called high energy ion implanters are known for forming relatively heavily doped n-wells and p-wells. It is also known to form deep buried wells using ion implanters.
Typically, the implanted regions are formed in a well-known manner by depositing photoresist on a surface of a semiconductor material, the photoresist forming a pattern such that the photoresist exposes selected regions of the surface of the semiconductor material so that ions expelled from the ion implanter can reach the surface of the semiconductor material and implantation of the ions can take place.
In this connection, a so-called “well proximity effect” is known to exist, whereby the operational performance, for example threshold voltage and drain current, of a transistor is affected by proximity of formation of the source or drain of the transistor to a well edge. The influence of the well edge parameter is understood to be caused by ions scattering from the edges of the photoresist, which become implanted in the surface of the exposed semiconductor material, thereby resulting in excess dopant near the border of the well and the photoresist: the “well edge”. Generally in line with Moore's law, the law that describes the long-term trend relating to the number of transistors that can be formed in an integrated circuit, the size of transistors being formed is decreasing and it has been found that the impact of the well effect is increasing as a consequence thereof.
Design engineers, mindful of the well proximity effect, therefore take precautions to obviate or at least mitigate the well proximity effect. In some instances, the design process involves making a conservative estimate of a safe distance from the well edge, or guard band, such that performance of devices formed outside the guard band are not affected by the well proximity effect. However, use of conservatively estimated guard bands results in transistors being formed further from the well edge than is necessary, a consequential result being that silicon “real estate” is unnecessarily wasted.
When designing integrated circuits, it is important to possess accurate models of transistors for electronic circuit simulation. To this end, for Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), it is known to use the so-called Berkeley Short-channel IGFET (Insulated Gate Field Effect Transistor) Model (BSIM), which characterises performance as a function of well distance, as described in Chapter 14 of the BSIM4.5.0 Manual available from University of California, Berkeley. Using the modelling information provided in this manual enables the safe well distance to be calculated with greater accuracy, thereby avoiding the need to estimate the guard band as mentioned above.
In such an implementation, the model described in the BSIM4.5.0 Manual is used in conjunction with a so-called “Optimiser” and a circuit simulator, for example Simulation Program with Integrated Circuit Emphasis (SPICE). In this respect, the Optimiser makes iterative changes to design parameters of an integrated circuit being designed and each iteration of the circuit design is passed to the circuit simulator for, inter alia, calculation of performance parameters of transistors, the results of the circuit simulation being passed back to the Optimiser for analysis and are used to guide generation of a subsequent iteration of the design parameters of the integrated circuit. In this regard, the Optimiser can iteratively change well distances iteratively until optimum well distances are determined.
The use of the Optimiser in conjunction with the circuit simulator is time consuming due to the number of iterations that need to be performed and the large number of parameters that potentially can be altered before an optimum solution can be found. As will be appreciated by the skilled person, such a solution is computationally complex, and the time consuming nature of the technique, contributes considerably to the fiscal cost of designing the integrated circuit.
An alternative solution is described in U.S. Pat. No. 7,089,513, which relates to a system that checks signal integrity (noise) of an integrated circuit design and changes edge distances of a Field Effect Transistor iteratively until signal integrity criteria are met. However, the system of U.S. Pat. No. 7,089,512 is limited to signal integrity performance and is also an iterative process that is still computationally expensive as explained above.